A semiconductor device may be used as a memory device, for example such as a NAND flash, and may be used as a switching device such as a low voltage transistor or a high voltage transistor.
A high voltage transistor may be included in a driving IC of a display device, and may have to withstand a high voltage.
FIG. 1 is an example diagram illustrating a related art high voltage transistor. FIG. 2 is an example sectional view taken along line I-I′ in the high voltage transistor of FIG. 1. FIG. 1 illustrates only one high voltage transistor, for convenience. However, a plurality of high voltage transistors as illustrated in FIG. 1 may be included in an integrated circuit (IC).
Reference letter A denotes a region in which a transistor may be formed and reference letter P denotes an ion implantation region for forming source/drain regions.
FIG. 1 may be considered an NMOS type, for convenience.
Referring to FIGS. 1 and 2, p type well 3 may be provided to form a transistor on semiconductor substrate 1. Hence, the substrate may be a p type doped silicon substrate.
A plurality of p type wells 3 or a plurality of n type wells may be formed on semiconductor substrate 1, and may be separated from each other by a prescribed interval (for example, a region in which a device isolation layer may be formed later). P type well 3 may be doped with p type impurities (such as boron (B)) and the n type well may be doped with n type impurities (such as arsenic (As)). An NMOS type high voltage transistor may be formed in p type well 3 and a PMOS type high voltage transistor may be formed in the n type well.
To form a well, doped impurities may have low density.
P type well 3 may be deeply formed in semiconductor substrate 1. Since p type well 3 may be deeply formed in semiconductor substrate 1, when a device is driven, an electric field may be dispersed to increase a breakdown voltage so as to withstand high voltage.
Device isolation layers 5 may be formed on semiconductor substrate 1 and may distinguish the wells from each other. Transistors may be insulated and separated from each other by device isolation layers 5. Device isolation layers 5 may be formed by a local of silicon (LOCOS) method or a shallow trench isolation (STI) method.
A silicon oxidation layer and a poly silicon may be laminated on semiconductor substrate 1 where device isolation layers 5 may be formed and may be patterned to form gate 7.
In p type well 3 of semiconductor substrate 1, source/drain regions (not shown) may be formed in the region excluding gate 7.
Although not shown in the drawing, threshold voltage Vt controlling ions may be thinly implanted into a surface of p type well 3. The threshold voltage controlling ions may be implanted into p type well 3 after forming device isolation layer 5.
The threshold voltage control ions may be distributed on a surface of p type well 3 but may move in accordance with external factors, for example such as heat.
That is, as illustrated in FIG. 3, when threshold voltage control ions 6 are heated, the threshold voltage control ions may not remain stationary around the surface of p type well 3. Some of the displaced ions may be found around the edges of the device isolation layers and, in severe cases, may penetrate device isolation layers 5.
In the related art high voltage transistor, threshold voltage Vt control ions may exist on a surface of the p type well and may freely move and penetrate the device isolation layers when heated. The threshold voltage control ions may become non-uniform, and may deteriorate operational characteristics of the device.
Therefore, according to the related art, although a desired amount of threshold voltage control ions may be implanted into p type well 3, threshold voltage control ions 6 may not be uniformly diffused in p type well 3, and doping density may be locally reduced. The non-uniform ion density distribution may cause a hump phenomenon, which may degrade the performance of a device.